Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:12.4 (ISE) - M.81d Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx9
Project ID (random number) 7e64947bca0e405d972361607b7f3a9f.50DC02AB374D4EEFB3AE0A0BE1B137BF.3 Target Package: tqg144
Registration ID 15690819_173552794_661 Target Speed: -3
Date Generated 2011-09-14T17:06:36 Tool Flow ISE
 
User Environment
OS Name Microsoft OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7-2620M CPU @ 2.70GHz CPU Speed 2693 MHz
OS Name Microsoft OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7-2620M CPU @ 2.70GHz CPU Speed 2693 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=2
  • 4-bit adder=2
 Comparators=5
  • 4-bit comparator greater=3
  • 4-bit comparator lessequal=1
  • 9-bit comparator greater=1
 Counters=5
  • 4-bit up counter=3
  • 8-bit up counter=1
  • 9-bit up counter=1
 FSMs=2 Multiplexers=29
  • 1-bit 2-to-1 multiplexer=3
  • 1-bit 8-to-1 multiplexer=1
  • 32-bit 2-to-1 multiplexer=16
  • 4-bit 2-to-1 multiplexer=7
  • 8-bit 2-to-1 multiplexer=2
 Registers=35
  • Flip-Flops=35
 		MiscellaneousStatistics
  • AGG_BONDED_IO=14
  • AGG_IO=14
  • AGG_LOCED_IO=13
  • AGG_SLICE=31
  • NUM_BONDED_IOB=14
  • NUM_BSFULL=50
  • NUM_BSLUTONLY=28
  • NUM_BSREGONLY=10
  • NUM_BSUSED=88
  • NUM_BUFG=2
  • NUM_LOCED_IOB=13
  • NUM_LOGIC_O5ANDO6=15
  • NUM_LOGIC_O5ONLY=13
  • NUM_LOGIC_O6ONLY=46
  • NUM_LUT_RT_DRIVES_CARRY4=2
  • NUM_LUT_RT_EXO6=2
  • NUM_LUT_RT_O6=13
  • NUM_SLICEL=9
  • NUM_SLICEM=1
  • NUM_SLICEX=21
  • NUM_SLICE_CARRY4=5
  • NUM_SLICE_CONTROLSET=12
  • NUM_SLICE_CYINIT=108
  • NUM_SLICE_F7MUX=4
  • NUM_SLICE_FF=67
  • NUM_SLICE_UNUSEDCTRL=6
  • NUM_SRL_O6ONLY=2
  • NUM_UNUSABLE_FF_BELS=35
 		NetStatistics
  • NumNets_Active=121
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=4
  • NumNodesOfType_Active_BOUNCEIN=20
  • NumNodesOfType_Active_BUFGOUT=2
  • NumNodesOfType_Active_BUFHINP2OUT=4
  • NumNodesOfType_Active_CLKPIN=25
  • NumNodesOfType_Active_CLKPINFEED=8
  • NumNodesOfType_Active_CNTRLPIN=30
  • NumNodesOfType_Active_DOUBLE=84
  • NumNodesOfType_Active_GENERIC=18
  • NumNodesOfType_Active_GLOBAL=24
  • NumNodesOfType_Active_INPUT=7
  • NumNodesOfType_Active_IOBIN2OUT=13
  • NumNodesOfType_Active_IOBOUTPUT=13
  • NumNodesOfType_Active_LUTINPUT=303
  • NumNodesOfType_Active_OUTBOUND=107
  • NumNodesOfType_Active_OUTPUT=106
  • NumNodesOfType_Active_PADINPUT=9
  • NumNodesOfType_Active_PADOUTPUT=5
  • NumNodesOfType_Active_PINBOUNCE=78
  • NumNodesOfType_Active_PINFEED=357
  • NumNodesOfType_Active_QUAD=49
  • NumNodesOfType_Active_REGINPUT=14
  • NumNodesOfType_Active_SINGLE=164
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_HVCCOUT=12
  • NumNodesOfType_Vcc_KVCCOUT=1
  • NumNodesOfType_Vcc_LUTINPUT=32
  • NumNodesOfType_Vcc_PINBOUNCE=1
  • NumNodesOfType_Vcc_PINFEED=32
 SiteStatistics
  • BUFG-BUFGMUX=2
  • IOB-IOBM=8
  • IOB-IOBS=6
  • SLICEL-SLICEM=1
  • SLICEX-SLICEL=5
  • SLICEX-SLICEM=4
 		SiteSummary
  • BUFG=2
  • BUFG_BUFG=2
  • CARRY4=5
  • FF_SR=10
  • HARD0=2
  • INVERTER=2
  • IOB=14
  • IOB_IMUX=5
  • IOB_INBUF=5
  • IOB_OUTBUF=9
  • LUT5=28
  • LUT6=76
  • LUT_OR_MEM6=2
  • PAD=14
  • PULL_OR_KEEP1=2
  • REG_SR=57
  • SELMUX2_1=4
  • SLICEL=9
  • SLICEM=1
  • SLICEX=21
 
Configuration Data
BUFGMUX
  • S=[S_INV:3] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:3]
  • S=[S_INV:3] [S:0]
 FF_SR
  • CK=[CK:10] [CK_INV:0]
  • SRINIT=[SRINIT0:10]
  • SYNC_ATTR=[ASYNC:10]
 IBUF_PAD
  • IOATTRBOX=[LVTTL:4] [LVCMOS33:1]
  • PULL=[PULLDOWN:3]
 IOB
  • O1=[O1_INV:0] [O1:9]
 IOB_OFF1
  • LATCH_OR_FF=[FF:8]
  • OFF1_INIT_ATTR=[INIT0:8]
  • OFF1_SR_ATTR=[SRLOW:8]
  • OFFATTRBOX=[SYNC:8]
 IOB_OUTBUF
  • DRIVEATTRBOX=[8:9]
  • SLEW=[SLOW:9]
  • SUSPEND=[3STATE:9]
 IOB_PAD
  • DRIVEATTRBOX=[8:9]
  • IOATTRBOX=[LVTTL:9]
  • SLEW=[SLOW:9]
 LUT_OR_MEM6
  • CLK=[CLK:2] [CLK_INV:0]
  • LUT_OR_MEM=[RAM:2]
  • RAMMODE=[SRL16:2]
 PULL_OR_KEEP1
  • PULLTYPE=[PULLDOWN:2]
 RAMB16
  • CLKA=[CLKA_INV:0] [CLKA:4]
  • CLKB=[CLKB_INV:0] [CLKB:4]
  • ENA=[ENA_INV:0] [ENA:4]
  • ENB=[ENB_INV:0] [ENB:4]
  • SSRA=[SSRA_INV:0] [SSRA:4]
  • SSRB=[SSRB_INV:0] [SSRB:4]
  • WEA=[WEA:4] [WEA_INV:0]
  • WEB=[WEB:4] [WEB_INV:0]
 RAMB16_RAMB16A
  • CLKA=[CLKA_INV:0] [CLKA:4]
  • ENA=[ENA_INV:0] [ENA:4]
  • PORTA_ATTR=[16384X1:4]
  • SSRA=[SSRA_INV:0] [SSRA:4]
  • WEA=[WEA:4] [WEA_INV:0]
  • WRITEMODEA=[WRITE_FIRST:4]
 RAMB16_RAMB16B
  • CLKB=[CLKB_INV:0] [CLKB:4]
  • ENB=[ENB_INV:0] [ENB:4]
  • PORTB_ATTR=[2048X9:4]
  • SSRB=[SSRB_INV:0] [SSRB:4]
  • WEB=[WEB:4] [WEB_INV:0]
  • WRITEMODEB=[WRITE_FIRST:4]
 REG_SR
  • CK=[CK:57] [CK_INV:0]
  • LATCH_OR_FF=[FF:57]
  • SRINIT=[SRINIT0:54] [SRINIT1:3]
  • SYNC_ATTR=[ASYNC:41] [SYNC:16]
 SLICEL
  • CLK=[CLK:7] [CLK_INV:0]
 SLICEL_CYMUXF
  • 0=[0:39] [0_INV:0]
  • 1=[1_INV:0] [1:39]
 SLICEL_CYMUXG
  • 0=[0:33] [0_INV:0]
 SLICEL_F5MUX
  • S0=[S0:34] [S0_INV:0]
 SLICEL_F6MUX
  • S0=[S0:4] [S0_INV:0]
 SLICEL_FFX
  • CE=[CE:67] [CE_INV:0]
  • CK=[CK:173] [CK_INV:0]
  • D=[D:173] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:137] [INIT1:36]
  • FFX_SR_ATTR=[SRLOW:152] [SRHIGH:21]
  • LATCH_OR_FF=[FF:173]
  • REV=[REV_INV:0] [REV:4]
  • SR=[SR:106] [SR_INV:16]
  • SYNC_ATTR=[ASYNC:100] [SYNC:73]
 SLICEL_FFY
  • CE=[CE:71] [CE_INV:0]
  • CK=[CK:193] [CK_INV:1]
  • D=[D:193] [D_INV:1]
  • FFY_INIT_ATTR=[INIT0:149] [INIT1:45]
  • FFY_SR_ATTR=[SRLOW:166] [SRHIGH:28]
  • LATCH_OR_FF=[FF:193] [LATCH:1]
  • SR=[SR:116] [SR_INV:19]
  • SYNC_ATTR=[ASYNC:103] [SYNC:91]
 SLICEL_XORF
  • 1=[1_INV:0] [1:37]
 SLICEM
  • CLK=[CLK:1] [CLK_INV:0]
 SLICEM_CYMUXF
  • 0=[0:11] [0_INV:0]
  • 1=[1_INV:0] [1:11]
 SLICEM_CYMUXG
  • 0=[0:7] [0_INV:0]
 SLICEM_F
  • DI=[DI:45] [DI_INV:0]
  • F_ATTR=[SHIFT_REG:45]
  • LUT_OR_MEM=[LUT:7] [RAM:45]
 SLICEM_F5MUX
  • S0=[S0:19] [S0_INV:0]
 SLICEM_F6MUX
  • S0=[S0:8] [S0_INV:0]
 SLICEM_FFX
  • CE=[CE:3] [CE_INV:0]
  • CK=[CK:22] [CK_INV:0]
  • D=[D:22] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:20] [INIT1:2]
  • FFX_SR_ATTR=[SRLOW:20] [SRHIGH:2]
  • LATCH_OR_FF=[FF:22]
  • SR=[SR:5] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:17] [SYNC:5]
 SLICEM_FFY
  • CK=[CK:20] [CK_INV:0]
  • D=[D:20] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:19] [INIT1:1]
  • FFY_SR_ATTR=[SRLOW:19] [SRHIGH:1]
  • LATCH_OR_FF=[FF:20]
  • SR=[SR:1] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:18] [SYNC:2]
 SLICEM_G
  • DI=[DI:65] [DI_INV:0]
  • G_ATTR=[SHIFT_REG:65]
  • LUT_OR_MEM=[LUT:3] [RAM:65]
 SLICEM_WSGEN
  • CK=[CK:65] [CK_INV:0]
  • SYNC_ATTR=[ASYNC:18]
  • WE=[WE_INV:0] [WE:65]
 SLICEM_XORF
  • 1=[1_INV:0] [1:5]
 SLICEX
  • CLK=[CLK:17] [CLK_INV:0]
 
Pin Data
BSCAN
  • DRCK1=1
  • SEL1=1
  • SHIFT=1
  • TDI=1
  • TDO1=1
  • TDO2=1
  • UPDATE=1
 BSCAN_BSCAN_BLACKBOX
  • DRCK1=1
  • SEL1=1
  • SHIFT=1
  • TDI=1
  • TDO1=1
  • TDO2=1
  • UPDATE=1
 BUFG
  • I0=2
  • O=2
 BUFGMUX
  • I0=3
  • O=3
  • S=3
 BUFGMUX_GCLKMUX
  • I0=3
  • OUT=3
  • S=3
 BUFGMUX_GCLK_BUFFER
  • IN=3
  • OUT=3
 BUFG_BUFG
  • I0=2
  • O=2
 CARRY4
  • CIN=3
  • CO3=3
  • CYINIT=2
  • DI0=4
  • DI1=4
  • DI2=4
  • DI3=3
  • O0=5
  • O1=4
  • O2=4
  • O3=4
  • S0=5
  • S1=4
  • S2=4
  • S3=4
 FF_SR
  • CE=7
  • CK=10
  • D=10
  • Q=10
  • SR=7
 HARD0
  • 0=2
 IBUF
  • I=5
  • PAD=5
 IBUF_INBUF
  • IN=5
  • OUT=5
 IBUF_PAD
  • PAD=5
 INVERTER
  • IN=2
  • OUT=2
 IOB
  • I=5
  • O=9
  • PAD=14
 IOB_IMUX
  • I=3
  • I_B=2
  • OUT=5
 IOB_INBUF
  • OUT=5
  • PAD=5
 IOB_OFF1
  • CK=8
  • D=8
  • Q=8
  • SR=8
 IOB_OUTBUF
  • IN=9
  • OUT=9
 IOB_PAD
  • PAD=9
 LUT5
  • A1=5
  • A2=11
  • A3=12
  • A4=7
  • A5=10
  • O5=28
 LUT6
  • A1=30
  • A2=37
  • A3=51
  • A4=73
  • A5=58
  • A6=73
  • O6=76
 LUT_OR_MEM6
  • A1=2
  • A2=2
  • A3=2
  • A4=2
  • A5=2
  • A6=2
  • CLK=2
  • DI2=2
  • O6=2
  • WE=2
 PAD
  • PAD=14
 PULL_OR_KEEP1
  • PAD=2
 RAMB16
  • ADDRA0=4
  • ADDRA1=4
  • ADDRA10=4
  • ADDRA11=4
  • ADDRA12=4
  • ADDRA13=4
  • ADDRA2=4
  • ADDRA3=4
  • ADDRA4=4
  • ADDRA5=4
  • ADDRA6=4
  • ADDRA7=4
  • ADDRA8=4
  • ADDRA9=4
  • ADDRB10=4
  • ADDRB11=4
  • ADDRB12=4
  • ADDRB13=4
  • ADDRB3=4
  • ADDRB4=4
  • ADDRB5=4
  • ADDRB6=4
  • ADDRB7=4
  • ADDRB8=4
  • ADDRB9=4
  • CLKA=4
  • CLKB=4
  • DIA0=4
  • DIB0=4
  • DIB1=4
  • DIB2=4
  • DIB3=4
  • DIB4=4
  • DIB5=4
  • DIB6=4
  • DIB7=4
  • DIPB0=4
  • DOA0=4
  • ENA=4
  • ENB=4
  • SSRA=4
  • SSRB=4
  • WEA=4
  • WEB=4
 RAMB16_RAMB16
  • ADDRA=4
  • ADDRB=4
  • DIA=4
  • DIB=4
  • DOA=4
  • DOB=4
 RAMB16_RAMB16A
  • ADDRA=4
  • ADDRA0=4
  • ADDRA1=4
  • ADDRA10=4
  • ADDRA11=4
  • ADDRA12=4
  • ADDRA13=4
  • ADDRA2=4
  • ADDRA3=4
  • ADDRA4=4
  • ADDRA5=4
  • ADDRA6=4
  • ADDRA7=4
  • ADDRA8=4
  • ADDRA9=4
  • CLKA=4
  • DIA=4
  • DIA0=4
  • DOA=4
  • DOA0=4
  • ENA=4
  • SSRA=4
  • WEA=4
 RAMB16_RAMB16B
  • ADDRB=4
  • ADDRB10=4
  • ADDRB11=4
  • ADDRB12=4
  • ADDRB13=4
  • ADDRB3=4
  • ADDRB4=4
  • ADDRB5=4
  • ADDRB6=4
  • ADDRB7=4
  • ADDRB8=4
  • ADDRB9=4
  • CLKB=4
  • DIB=4
  • DIB0=4
  • DIB1=4
  • DIB2=4
  • DIB3=4
  • DIB4=4
  • DIB5=4
  • DIB6=4
  • DIB7=4
  • DIPB0=4
  • DOB=4
  • ENB=4
  • SSRB=4
  • WEB=4
 REG_SR
  • CE=37
  • CK=57
  • D=57
  • Q=57
  • SR=41
 SELMUX2_1
  • 0=4
  • 1=4
  • OUT=4
  • S0=4
 SLICEL
  • A1=1
  • A2=1
  • A3=1
  • A4=5
  • A5=2
  • A6=5
  • AMUX=1
  • AQ=5
  • B=1
  • B3=1
  • B4=5
  • B5=1
  • B6=5
  • BQ=4
  • C1=3
  • C2=3
  • C3=4
  • C4=8
  • C5=4
  • C6=8
  • CE=2
  • CIN=3
  • CLK=7
  • CMUX=3
  • COUT=3
  • CQ=5
  • CX=4
  • D1=2
  • D2=2
  • D3=4
  • D4=8
  • D5=4
  • D6=7
  • DQ=4
  • SR=6
 SLICEL_C1VDD
  • 1=2
 SLICEL_CYMUXF
  • 0=39
  • 1=39
  • OUT=39
  • S0=39
 SLICEL_CYMUXG
  • 0=33
  • 1=33
  • OUT=33
  • S0=33
 SLICEL_F
  • A1=196
  • A2=158
  • A3=115
  • A4=88
  • D=197
 SLICEL_F5MUX
  • F=34
  • G=34
  • OUT=34
  • S0=34
 SLICEL_F6MUX
  • 0=4
  • 1=4
  • OUT=4
  • S0=4
 SLICEL_FFX
  • CE=67
  • CK=173
  • D=173
  • Q=173
  • REV=4
  • SR=122
 SLICEL_FFY
  • CE=71
  • CK=194
  • D=194
  • Q=194
  • SR=135
 SLICEL_G
  • A1=199
  • A2=165
  • A3=133
  • A4=74
  • D=199
 SLICEL_GNDF
  • 0=37
 SLICEL_GNDG
  • 0=33
 SLICEL_XORF
  • 0=37
  • 1=37
  • O=37
 SLICEL_XORG
  • 0=34
  • 1=34
  • O=34
 SLICEM
  • B1=1
  • B2=1
  • B3=1
  • B4=1
  • B5=1
  • B6=1
  • BI=1
  • BQ=1
  • C1=1
  • C2=1
  • C3=1
  • C4=1
  • C5=1
  • C6=1
  • CE=1
  • CI=1
  • CLK=1
  • CQ=1
  • DQ=1
  • DX=1
 SLICEM_CYMUXF
  • 0=11
  • 1=11
  • OUT=11
  • S0=11
 SLICEM_CYMUXG
  • 0=7
  • 1=10
  • OUT=10
  • S0=10
 SLICEM_F
  • A1=47
  • A2=47
  • A3=47
  • A4=45
  • D=52
  • DI=45
  • WS=45
 SLICEM_F5MUX
  • F=19
  • G=19
  • OUT=19
  • S0=19
 SLICEM_F6MUX
  • 0=8
  • 1=8
  • OUT=8
  • S0=8
 SLICEM_FFX
  • CE=3
  • CK=22
  • D=22
  • Q=22
  • SR=5
 SLICEM_FFY
  • CK=20
  • D=20
  • Q=20
  • SR=1
 SLICEM_FMC15_BLACKBOX
  • MC15=24
  • WS2=24
 SLICEM_G
  • A1=68
  • A2=68
  • A3=68
  • A4=66
  • D=64
  • DI=65
  • WS=65
 SLICEM_GMC15_BLACKBOX
  • MC15=46
  • WS2=46
 SLICEM_GNDF
  • 0=11
 SLICEM_GNDG
  • 0=7
 SLICEM_VDDG
  • 1=3
 SLICEM_WSGEN
  • CK=65
  • WE=65
  • WSF=45
  • WSG=65
 SLICEM_XORF
  • 0=5
  • 1=5
  • O=5
 SLICEM_YBUSED
  • 0=18
  • OUT=18
 SLICEX
  • A=5
  • A1=4
  • A2=5
  • A3=9
  • A4=11
  • A5=10
  • A6=10
  • AMUX=4
  • AQ=9
  • AX=3
  • B=2
  • B1=8
  • B2=10
  • B3=11
  • B4=12
  • B5=11
  • B6=12
  • BMUX=3
  • BQ=12
  • BX=2
  • C=4
  • C1=9
  • C2=12
  • C3=12
  • C4=13
  • C5=14
  • C6=14
  • CE=11
  • CLK=17
  • CMUX=2
  • CQ=12
  • CX=2
  • D=11
  • D1=6
  • D2=9
  • D3=10
  • D4=11
  • D5=12
  • D6=12
  • DMUX=4
  • DQ=3
  • DX=2
  • SR=11
 
Tool Usage
Command Line History
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s500e-fg320-4 -cm area -pr off -k 4 -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s500e-fg320-4 -cm area -pr off -k 4 -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s500e-fg320-4 -cm area -pr off -k 4 -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s500e-fg320-4 -cm area -pr off -k 4 -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
_impact 11 9 0 0 0 0 0
arwz 7 7 0 0 0 0 0
bitgen 19 19 0 0 0 0 0
cse_server 8 8 0 0 0 0 0
edif2ngd 20 20 0 0 0 0 0
elfcheck 31 31 0 0 0 0 0
libgen 4 4 0 0 0 0 0
map 32 24 0 0 0 0 0
netgen 14 14 0 0 0 0 0
ngc2edif 3 3 0 0 0 0 0
ngcbuild 47 47 0 0 0 0 0
ngdbuild 33 33 0 0 0 0 0
obngc 3 3 0 0 0 0 0
par 24 24 0 0 0 0 0
platgen 4 4 0 0 0 0 0
psf2Edward 5 5 0 0 0 0 0
trce 22 22 0 0 0 0 0
xawinfo 9 9 0 0 0 0 0
xbash 2 1 0 0 0 0 0
xdsgen 4 4 0 0 0 0 0
xps 20 11 0 0 0 0 0
xst 98 97 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/cgn_c_cust_gui_overview.htm ( 1 )
 
Project Statistics
PROP_CompxlibOverwriteLib=true PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PostTrceFastPath=false PROP_PreTrceFastPath=false
PROP_PropSpecInProjFile=Store all values PROP_SimModelInsertBuffersPulseSwallow=false
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_XPowerOptLoadXMLFile=changed
PROP_XPowerOptOutputFile=changed PROP_intProjectCreationTimestamp=2011-06-22T21:01:01
PROP_intWbtProjectID=50DC02AB374D4EEFB3AE0A0BE1B137BF PROP_intWbtProjectIteration=3
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_AutoTop=true PROP_DevFamily=Spartan6
PROP_MapEffortLevel=Standard PROP_DevDevice=xc6slx9
PROP_DevFamilyPMName=spartan6 PROP_DevPackage=tqg144
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-3
PROP_PreferredLanguage=Verilog FILE_UCF=1
FILE_VERILOG=7
 
PlanAhead Usage
Project Data
SrcSetCount=1 ConstraintSetCount=1 DesignMode=RTL SynthesisStrategy=PlanAhead Defaults
ImplStrategy=ISE Defaults
Java Command Handlers
AddConstraint=1 AddCreateSrc=1 ConfigureBitgenRun=1 ConfigureImplRun=2
ConfigureSynthRun=2 CoreView=2 CreateHistogram=1 CreateProject=2
ImportTiming=1 ReportTiming=2 RunDesignAhead=2 RunElaborate=1
RunImplementation=2 RunNoiseAnalysis=1 RunSynthesis=3 ShowView=5
ViewLayoutCmd=3 ViewTaskImplementedDesign=1 ViewTaskProjectManager=2
Other
GuiMode=3 BatchMode=0 TclMode=0 ISEMode=0
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=5 NGDBUILD_NUM_FDC=7
NGDBUILD_NUM_FDCE=24 NGDBUILD_NUM_FDE=14 NGDBUILD_NUM_FDP=1 NGDBUILD_NUM_FDR=8
NGDBUILD_NUM_FDRE=6 NGDBUILD_NUM_FDSE=2 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=4
NGDBUILD_NUM_INV=5 NGDBUILD_NUM_LUT1=15 NGDBUILD_NUM_LUT2=7 NGDBUILD_NUM_LUT3=13
NGDBUILD_NUM_LUT4=14 NGDBUILD_NUM_LUT5=10 NGDBUILD_NUM_LUT6=27 NGDBUILD_NUM_MUXCY=15
NGDBUILD_NUM_MUXF7=4 NGDBUILD_NUM_OBUF=9 NGDBUILD_NUM_SRLC16E=2 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=17
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_FD=5 NGDBUILD_NUM_FDC=7 NGDBUILD_NUM_FDCE=24
NGDBUILD_NUM_FDE=14 NGDBUILD_NUM_FDP=1 NGDBUILD_NUM_FDR=8 NGDBUILD_NUM_FDRE=6
NGDBUILD_NUM_FDSE=2 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=4 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=5 NGDBUILD_NUM_LUT1=15 NGDBUILD_NUM_LUT2=7 NGDBUILD_NUM_LUT3=13
NGDBUILD_NUM_LUT4=14 NGDBUILD_NUM_LUT5=10 NGDBUILD_NUM_LUT6=27 NGDBUILD_NUM_MUXCY=15
NGDBUILD_NUM_MUXF7=4 NGDBUILD_NUM_OBUF=9 NGDBUILD_NUM_PULLDOWN=2 NGDBUILD_NUM_SRLC16E=2
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=17